简述Σ-ΔADC(第一部分)

技术分类: 模拟设计  | 2008-01-22
来源:EDN | 作者:Bonnie Baker

  At the modulator output, the digital filter addresses high-frequency noise and high-speed-sample-rate issues. Because the signal now resides in the digital domain, you can apply a lowpass digital filter to attenuate the higher frequency noise and a decimator filter to slow down the out

put-data rate. The digital/decimator filter samples and filters the modulator’s stream of 1-bit codes and creates a slower multibit code.

  Although most converters have only one sample rate, delta-sigma converters have two: the input sampling rate and the output-data rate. The ratio of these two meaningful variables defines the system’s decimation ratio. A strong relationship exists between the decimation ratio and the converter’s effective resolution. A future column will examine how the modulator, digital/decimator filter, and adjustable decimation ratio work.

  Reference

  Baker, R Jacob, CMOS Mixed-Signal Circuit Design: Volume II, John Wiley & Sons, 2002, ISBN: 0471227544.

  英文原文地址:http://www.edn.com/article/CA6512148.html

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