iPhone拆解:不仅仅是个电话

技术分类: 消费电子设计  | 2007-08-06
作者:EDN | Brian Dipert

  The main board assembly, swathed in EMI-shielding material, is a two-PCB (digital and RF) sandwich, which you can see between the camera module and antenna in the overview photo. Note that in the images that follow, the background grid dimension is 1 cm. One side of the digital board is dominated by a 4- or 8-Gbyte NAND flash chip (depending on the iPhone model), on the PCB's left side. If you visit Samsung's website, the largest device you'll find listed there is a 32-Gbit (4-Gbyte) NAND flash memory, and only single bit-per-cell devices are represented. While Samsung could get to 8 Gbytes in a single package by implementing a two-die arrangement, I've long suspected (and other teardowns have confirmed) that Apple is an early customer for S

amsung's nascent MLC (multilevel-cell, aka two-bit-per-cell) NAND-flash-memory program. This is the same NAND flash memory used in the iPod nano.

  The other dominant IC on that same side of the digital PCB is an Apple-labeled applications processor on the right, with a volatile memory underneath it in a two-package stack. Die-level analysis by Portelligent and Semiconductor Insights has confirmed that the applications processor is a Samsung design, thereby following in the footsteps of Samsung's first CPU design win with Apple in the second-generation iPod nano. A specific part number is unknown at this time; the IC may not (yet?) be available in the open market. However, hackers' analysis of the iPhone's recovery firmware has uncovered some interesting CPU specifications:

  * ARM1176JZF with TrustZone, believed to be running at upwards of 600 MHz
    * ARM Intelligent Energy Manager
    * 16-kbyte/16-kbyte code/data cache
    * Vector floating point coprocessor
    * ARM Jazelle-enabled for embedded-Java execution
    * SIMD high performance integer CPU with an eight-stage pipeline, capable of 675 Dhrystones/sec and 2.1 MIPS
    * 0.45 mW/MHz power draw (with cache).

  Firmware decoding also points to the Samsung CPU's inclusion of an Imagination Technologies-licensed graphics core, which if true would be quite ironic given my conversation with a company representative during January's Consumer Electronics Show.

  What about that "volatile memory" I mentioned? It's a source of disagreement between Semiconductor Insights and Portelligent. Semiconductor Insight's video claims that the chip is an SRAM, but Portelligent is adamant that its die inspection identifies the device as a mobile (that is, low-power) DDR SDRAM.

  Asked about this memory device and another I'll discuss a bit later, Don Stroud, Portelligent's director of business development, said, "We have reviewed both of the memory chips in question and still believe our assessments are correct….We did a detailed review of the package marking and then extracted the die from their respective packages to get the die markings. So, package and die markings, coupled with data sheets, make us very confident of our assessments. It would be interesting to pose the same questions to others who have analyzed the iPhone, and to know what manner of verification they employed to derive their conclusions." Translation: Touché, Semiconductor Insights!

  I haven't seen the die plot myself, so I can't say for sure what memory technology's inside, but the cost-per-bit advantage of DRAM over SRAM is indisputable. And given the greater-than-50% gross profit margin that Apple's reportedly accruing, controlling bill-of-materials costs is obviously critical to the company. With that said, you can't overlook DRAM's higher average power consumption than SRAM, due to the need for periodic refresh, although low power-tuned SRAMs tend not to have significantly faster access times (random or sequential) than their DRAM peers. A feature article published nearly four years ago goes into DRAM-versus-SRAM tradeoffs in great detail, and I commend it to your inspection if you want to learn about this topic in greater depth.

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