McCanny: The issue of right first time has been around for a lot of generations of technology.
Q: But now it’s a lot more expensive to make a mistake, right?
McCanny: It’s expensive and the chances of getting it right the first time are going down. It’s a combination of a lot of factors. What we can try to do to solve this is come up with models that bound the problem. There are corner models, which are the most extreme things that could ever occur, and then you try to design to t
hat. That was okay for a few generations of technology, but the bounds that are created are to make sure that you meet timing. Assuming you meet your functionality, which is another problem, it’s now more than meeting timing. You also have to manage leakage power, and if you’re over-bounding the problem in one dimension you blow away all your targets in the other dimension. It’s not just having a working part. It’s having a working part that’s marketable. If it’s functional and meets timing, it still may not meet the power budget. You have make tradeoffs. What it comes down to is that the corner model doesn’t work anymore.
Hu: We have been working on the back-end design. There is a key issue at advanced technology nodes. With the 193 nanometer stepper, when you try to produce something at 45 nanometers or 32 nanometers, the wavelength issue is out of control. On the manufacturing side, a lot of things have been taking place. With [optical-proximity correction], when you try to make your final image on silicon it’s more predictable. Otherwise, a lot of lines can break because of the wavelength issue. On the foundry side, companies like TSMC have done a lot to qualify the prediction. If you cannot reproduce the shift, you cannot predict anything.
Hamid: The predictability problem is huge. Chips are expensive to develop and the market is competitive. If you mess it up, someone else eats your lunch. We have pretty mature flows to get us from RTL to layout. The areas where pr
edictability suffers are in the back end, relating the layout to the process technologies, and the front end, trying to get the functional verification right. We’re spending at least 70 percent of our effort trying to get verification right, and yet we are re-spinning at least three out of four of our chips because we didn’t do it right. This has all kinds of cascade effects on predictability. We have to get out of random testing, hoping to all of our bugs out that way, and find solutions to cr
eating targeted test cases that will hunt down, find and kill these bugs and improve predictability.
Q: Is there a solution to these problems?
Quan: As part of the ecosystem—the design companies, EDA, the service companies and the foundries—we have to work toward a solution to solve these areas. As Jim (McCanny) said, one of the methodologies today, especially for the digital technologies, is using corner models. That’s trying to predict the worst case, but when you put everything in corners you’re over-designing. You draw out a very big box even though you never get to those corners. On the ASIC methodology side, we’re now looking at statistical modeling. You describe the reliability of the process in a true statistical manner with the proper distribution. I believe that will help ASIC designers achieve faster timing closure and allow us to fully leverage processes. On the back end, you think you’re drawing a shape but through the lithography effect the shape comes out differently. Is that affecting the electrical circuits? Probably not so far. But as we go to smaller and smaller geometries, the shape will create differences in electrical performance. The ability to predict the shape coming out and incorporate it earlier into the design or the timing model or the SPICE net list for the mixed signal and analog designers is very important.