引自EDN博客:
levension
// *********************************************************************
// 数字钟VerilogHDL代码
//2007.7.27 by Levension @SCUT
//参考网上范例修改的
// *********************************************************************
module clock_main(clk_4Hz,mode,sel,add,alert,hour,min,sec,msec,LD);
input clk_4Hz;
input mode,sel,add;
output alert;
output [7:0] hour,min,sec,msec;
output [2:0] LD;
reg[7:0] hour,min,sec,msec,thour,tmin,tsec,ahour,amin,asec;
reg ath,atm,ats,aah,aam,aas;
reg [2:0]LD;
re
g clk_1Hz,start,m_clk,h_clk;
reg [1:0] cnt,Nmode,Bsel;
wire ct1,ct2,ct3,cta,ctb,ctc;
parameter TIMER="2"'b00,
SETTM="2"'b01,
ALERT="2"'b10;
always @(posedge clk_4Hz) //产生1Hz
begin
cnt<=cnt==3?0:cnt+1;
if(cnt<2) clk_1Hz=0;
else clk_1Hz=1;
end
always @(negedge mode) //模式选择
begin
if(Nmode==2'd2) Nmode<=2'd0;
else Nmode<=Nmode+1;
end
always
case(Nmode) //发光二极管指示模式
TIMER:LD<=3'b110;
SETTM:LD<=3'b101;
ALERT:LD<=3'b011;
endcase
always @(negedge sel) //调整位置选择
if(Nmode==SETTM||Nmode==ALERT)
begin
if(Bsel==2'd2) Bsel<=2'd0;
else Bsel<=Bsel+1;
end
always //add调整信号
begin
case(Nmode)
SETTM: //设置时间
begin
case(Bsel)
&