首先先用tt做电路仿真。考虑Vt有+20% (slow)和-20% (fast),需要对工艺角考虑，FF，SS，FS，SF。除Vt，其他工艺参数也会有变化。
7. Its thumb rule that poly resistance has a 20% process variation whereas well resistance has got 10%. But the poly resistance has got lower temperature coefficient and lower Sheet Resistance than well resistance So we choose the resistance type depending upon the requirements. Poly Capacitance has got a process variation of 10%.
多晶硅电阻大约有20%的工艺变化，而阱区电阻变化约为10%。但多晶硅电阻有较低的温度系数和低的方块电阻，应根据需要来选择电阻。多晶硅电容约有10%工艺变化。
8. One should also check the circuit performance with the temperature variation. We usually do it for the range of -40C to 85C.
需考虑温度变化对电路性能的影响，通常在-40C到85C范围。
9. One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells.
有覆盖金属层或阱区时，须考虑寄生电容。
10. In Layout, all transistors should be placed in one direction, to provide the same environment to all the transistors.
Layout中，所有晶体管统一摆放方向，使有相同的环境。
11. One should place all transistor in layout with a due care to the pin position before start routing them.
在对晶体管布局布线之前，考虑Pin的位置。
12. One should always use the Metal 1 for horizontal routing and Metal 2 for the vertical routing as far as possible.
尽量使用metal1横向布线，metal2纵向布线半导体。
13. One should never use POLY as routing layer when the interconnects carries a current. One can have a short gate connection using poly.
在互连用来传送电流时，不要用Poly来做互连。可以用poly做短的栅连接。
14. One should try to avoid running metal over poly gate. As this cause to increase in parasitic capacitance.
避免金属在多晶硅栅上走线，会增加寄生电容。
15. Current in all the transistor and resistor part should flow in the same direction.
所有晶体管和电阻有相同的电流走向。
16. One should do the Power(VDD & GND) routing in top layer metal (metal5 only). Because Top layer metals are usually thicker and wider and so has low resistance.