在最上层金属做电源（VDD和GND）布线。因为最上层金属通常更厚、更宽，因而电阻较小。
17. One should always merge drain and source of transistor (of same type) connected together.
merge连接的Source和Drain。
18. To minimize the process variation in the Resistor value one should always take the resistor’s width three to four times of the default value. we do it to decrease the value of differential of R(L)
为减小工艺变化对电阻影响，应使电阻的宽度为默认值的3-4倍半导体。
19. One should cover the resistance with metal layer, to avoid the damaged during the wafer level testing.
用金属覆盖电阻，避免wafer级测试时的损伤。
20. One should always make a Common Centroid structure for the matched transistor in the layout. Each differential pair transistor should be divide into four transistors and should be placed in two rows common centroid structure. One may use the linear common centroid structure for the current mirror circuit.
对匹配的晶体管用共中心的结构
*差分对管，分割为4管，2*2排列，共中心
可用线形共中心
21. It’s advisable to put a dummy layers around the resistance and the capacitance to avoid the erosion at the time of etching.
建议在电阻和电容周围作dummy。
22. One should always have a Guard Ring around the differential pair.
在差分对周围作保护环。
23. Always put a Guard Ring around the N-well and P-well.
在N阱和P阱作保护环。
24. Thumb rule for the metal current density is 0.8mA/um. It’s larger for the top most metal layer.
金属电流密度0.8mA/um，最上层金属可以更大半导体。
25. To avoid the Latch-up, one should always make the PN junction reverse biased i.e. In NWELL should be connected to positive power supply (VDD) and PWELL should be connected to negative power supply (GND). Designers do it to make the leakage current small.
为避免Latch-up，应使PN结反偏，如N-Well应连到正电源，P-Well应连到负电源。这样可减小漏电。
26. It’s always a good practice to use an info-text layer to put the name of the device on the top of it in layout and have a net-name for every nets in schematic. Designer should put the pin name on the top of the pin with same metal-txt layer because hercue ls takes the net-name from metal-txt only whereas Diva takes from the pin-name.